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SI5020C-BA
Si5020 MICRO PCB W I T H S 3 0 5 0 FOOTPRINT
Features
!
Supports substitution of the Si5020 in systems designed for AMCC S3050 footprint ! Simplifies evaluation of the Si5020 device
!
DSPLLTM technology eliminates external loop filter components ! Excellent jitter generation performance: 3.0 mUIrms (typical) ! Low power consumption: 108 mA at OC-48 (typical) ! Wide supply voltage range: 3 to 6 V
Ordering Information: See page 11.
Applications
!
Replacement for S3050 ! In-system evaluation of the Si5020 SiPHYTM multi-rate SONET/SDH clock and data recovery IC
Pin Assignments SI5020C-BA
RATESEL0 VCC VEE VEE
26
NC
NC
The SI5020C-BA is a micro printed circuit board (PCB) that allows use of the Si5020 clock and data recovery (CDR) device in communications systems originally designed for the AMCC S3050. No system circuit board changes are necessary because the micro PCB is pin-compatible with the S3050. The Si5020 device offers significant advantages in jitter performance, power dissipation, ease of use, and size over competing CDRs. The Si5020 incorporates Silicon Laboratories' DSPLLTM technology for improved performance and ease of use. DSPLL technology eliminates external loop filter components and their associated noise entry points, thus making the Si5020 CDR less susceptible to board-level interaction and helping to ensure optimal jitter performance.
32
31
29
30
27
28
NC
NC VCC VEE VEE SERDATIP SERDATIN NC REFCLKP
25
VCC
Description
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
11 10 13 12 14 15 16
RATESEL1 SERCLKOP SERCLKON VEE NC SERDATOP SERDATON NC
9
NC
NC
VCC
REFCLKN
VCC
VEE
VEE
Top View
Functional Block Diagram
RATESEL0 LOCKDET RATESEL1 RATESEL1 RATESEL0 LOL SERDATIP SERDATIN DIN+ DIN-
Inverter
DOUT+ DOUT- SERDATOP SERDATON
PWRDN/CAL
Si5020 CDR
REXT GND VDD
REFCLKP REFCLKN VCC IN GND POK OUT
REFCLK+ REFCLK-
CLKOUT+ CLKOUT-
SERCLKOP SERCLKON
VEE
Regulator
Rev. 1.0 3/04
Copyright (c) 2004 by Silicon Laboratories
SI5020C-BA-DS10
LOCKDET
SI5020C-BA
2
Rev. 1.0
SI5020C-BA TABLE O F CONTENTS
Section Page
SI5020C-BA Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Si5020 CDR Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Voltage Regulator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Rate Select Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Lock Detect Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 High-Speed Serial Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Recovered Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Recovered Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Soldering/Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pin Descriptions: SI5020C-BA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package Outline: SI5020C-BA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Rev. 1.0
3
U5 VCC INV 2 A NC 3 MC74VHC1GT04 GND Y 1 2 7 11 14 4 5
VDDA VDDB VDDC VDDD
REXT 3 8 18
GNDA GNDB GNDC
4
5.0V
5.0V DC 2.5V DC
U3
1
IN
OUT
5
LOCKDET
2
GND R2 0402 10k (1%) U1
SI5020C-BA
3
EN
POK
4
MAX8875EUK25 6
C2 0603 0.022uF SERDATIP DIN+ DOUTDOUT+ 13 DINSERDATIN C1 0805 4.7uF 6.3V 4 REFCLK+ CLKOUTCLKOUT+ REFCLK16 17 5 10 9 12 SERDATON SERDATOP
SI5020C-BA Schematic Diagram
RATESEL0 RATESEL1 RATESEL1 RATESEL0 PWRDN/CAL LOL
20 19 15
Rev. 1.0
REFCLKP REFCLKN 1 Si5018/20 R1 0402 10k (1%)
SERCLKON SERCLKOP
System GND
SI5020C-BA
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature SI5020C-BA Supply Voltage2 Symbol TA VCC Test Condition Min1 -40 3.0 Typ 25 5.0 Max1 85 6.0 Unit C V
Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated. 2. The SI5020C-BA specifications are guaranteed when using the recommended application circuit (including component tolerance) of "Typical Application Schematic" on page 6.
Table 2. DC Characteristics
(VCC = 5.0 V 5%, TA = -40 to 85 C)
Parameter Supply Current OC-48 GbE OC-12 OC-3 Power Dissipation OC-48 GbE OC-12 OC-3
Symbol ICC
Test Condition
Min -- -- -- -- -- -- -- --
Typ 108 113 117 124 540 566 586 620
Max -- -- -- -- -- -- -- --
Unit mA
mW
Table 3. Absolute Maximum Ratings
Parameter DC Supply Voltage LVTTL Input Voltage Storage Temperature Range Lead Temperature (soldering 10 s) ESD HBM Tolerance (100 pf, 1.5 k) Symbol VCC VDIG TSTG Value -0.5 to 7.0 -0.3 to 3.6 -55 to 150 300 1 Unit V V C C kV
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 1.0
5
SI5020C-BA
Typical Application Schematic
LVTTL Control Inputs Lock Indicator
RATESEL0
0.1 F High Speed Serial Input 0.1 F 0.1 F System Reference Clock 0.1 F REFCLKP REFCLKN SERDATIP SERDATIN
RATESEL1
LOCKDET
0.1 F SERDATOP SERDATON Recovered Data 0.1 F 0.1 F SERCLKOP SERCLKON Recovered Clock 0.1 F
SI5020C-BA
VCC
4.7 F VCC
6
Rev. 1.0
VEE
SI5020C-BA
Functional Description
The SI5020C-BA is a micro PCB that adapts the Si5020 device to meet the footprint and essential functionality of the AMCC S3050 device. It allows substitution of the Si5020 device in systems designed for the S3050. The SI5020C-BA board is comprised of the Si5020 CDR device and support circuitry for voltage regulation, initiation of calibration, and lock detect signal polarity inversion. A schematic diagram for the SI5020C-BA is given in the "SI5020C-BA Schematic Diagram" on page 4.
Table 4. Multi-Rate Configuration
RATESEL [1:0] 00 10 01 11 SONET/ SDH 2.488 Gbps 1.244 Gbps 622.08 Mbps 155.52 Mbps Gigabit OC-48 w/ Ethernet 15/14 FEC -- 1.25 Gbps -- -- 2.67 Gbps -- -- --
Si5020 CDR Device
Please refer to the Si5020 data sheet for detailed operation and performance data for the Si5020 CDR device. Relative to the Si5020, the S3050 RATESEL pins are reversed such that RATESEL0 on the Si5020 corresponds to RATESEL1 on the S3050. This swapped mapping is handled on the SI5020C-BA such that the RATESEL inputs on the S3050-BA board match those of the S3050 device.
Voltage Regulator Circuit
To account for the power supply requirement differences between the S3050 and the Si5020, a lowdropout linear voltage regulator is used to regulate the SI5020C-BA board's 5 V supply input down to the 2.5 V supply used for the Si5020.
Lock Detect Output
Lock detection is performed by the Si5020 device. The LOL signal from the Si5020 device has an inverted polarity relative to that of the S3050. An inverting/levelshifting buffer is utilized on the SI5020C-BA to provide a TTL compatible LOCKDET output from the board that matches the S3050 output signal polarity. This signal will go high when the SI5020C-BA locks to the incoming serial data.
Generation of the PWRDN/CAL Signal
To achieve optimal jitter performance, the Si5020 device provides an internal self-calibration capability. Selfcalibration optimizes loop gain parameters within the Si5020 DSPLL. Self-calibration is initiated by the falling edge of the Si5020 device PWRDN/CAL input signal. On the SI5020C-BA board, the Si5020 PWRDN/CAL signal is driven from the voltage regulator POK output signal through series capacitor C2. This circuit is identical to one described within Silicon Laboratories' application note AN42: "Controlling DSPLLTM Selfcalibration for the Si5020/5018/5010 CDR Devices and Si531x Clock Multiplier/Regenerator Devices"
Reference Clock Input
The reference clock inputs (REFCLKP/N) provide coarse frequency information to the Si5020. This frequency information is used to identify the incoming serial data frequency and provide lock detection. The supported frequencies for OC-48/12/3 are 155.52, 77.76, and 19.44 MHz. These frequencies are automatically detected within the Si5020 and no digital control inputs are required for clock frequency selection. The REFCLKP/N inputs are internally biased to an input common mode voltage of 2.0 V and provide 100 lineto-line termination. AC coupling is recommended as the simplest coupling approach. (See "Typical Application Schematic" on page 6.) Full details on the REFCLKP/N pins can be found in the Si5020 data sheet REFCLK pin descriptions.
Rate Select Inputs
The RATESEL pins are used to set operating data rates for the SI5020C-BA. These pins set internal frequency dividers in the Si5020 device. The RATESEL pin settings for each data rate are given in Table 4
Rev. 1.0
7
SI5020C-BA
High-Speed Serial Input
The high-speed serial data inputs (SERDATIP/N) provide data to the Si5020 for clock and data recovery. The SERDATIP/N inputs are internally biased to an input common mode voltage of 2.0 V and provide 100 line-to-line termination. AC coupling is recommended as the simplest coupling approach. (See "Typical Application Schematic" on page 6.) Full details on the SERDATIP/N pins can be found in the Si5020 data sheet DIN pin descriptions. the reflow process.
Recovered Data Output
The recovered data outputs (SERDATOP/N) transmit the recovered serial data. These outputs are time aligned to the recovered clock outputs. The SERDATOP/N outputs are current mode logic (CML) outputs. AC coupling is recommended as the simplest coupling approach. (See "Typical Application Schematic" on page 6.) Full details on the SERDATOP/ N pins can be found in the Si5020 data sheet DOUT pin descriptions.
Recovered Clock Output
The recovered clock outputs (SERCLKOP/N) transmit the clock recovered from the serial data. These outputs are time aligned to the recovered data outputs. The SERCLKOP/N outputs are CML outputs. AC coupling is recommended as the simplest coupling approach. (See "Typical Application Schematic" on page 6.) Full details on the SERCLKOP/N pins can be found in the Si5020 data sheet CLKOUT pin descriptions.
Soldering/Assembly
The SI5020C-BA employs a minimal lead length which is significantly different from a QFP lead. Despite the lead differences, handling of the SI5020C-BA is similar to handling of a QFP. Automation of the alignment and soldering processes will simplify the attachment. Alignment can be accomplished using standard pickand-place machines. Set the pick point to the center of the Si5020 device; this point is marked within the mechanical drawing. (See Figure 2 on page 12.) Once aligned, soldering the SI5020C-BA to another PCB is best accomplished using solder paste and a reflow chamber. Once the SI5020C-BA is placed upon the solder paste the reflow process can occur. The SI5020C-BA evaluation board itself has been assembled using 220 C solder in order maintain the locations of the Si5020 device, voltage regulator, inverter, and passive components on the board during
8
Rev. 1.0
SI5020C-BA
Pin Descriptions: SI5020C-BA
RATESEL0
VCC
VEE
32
31
30
29
28
27
VEE
26
NC
NC
NC
NC VCC VEE VEE SERDATIP SERDATIN NC REFCLKP
25
VCC
1 2 3 4 5 6 7 8
13 11 10 12 14 15 16
24 23 22 21 20 19 18 17
RATESEL1 SERCLKOP SERCLKON VEE NC SERDATOP SERDATON NC
REFCLKN
9
VCC
VCC
NC
NC
VEE
VEE
Top View
Figure 1. SI5020C-BA Pin Configuration
Pin # 1, 7, 10, 11, 17, 20, 27, 28, 32 2, 12, 14, 25, 29 3, 4, 13, 15, 21, 26, 30 5, 6 8, 9
Pin Name NC
I/O
Signal Level
LOCKDET
Description No Connect. These pins are not used by the SI5020C-BA board. The pins are not connected to circuitry on the board.
VCC VEE SERDATIP, SERDATIN REFCLKP, REFCLKN LOCKDET I I
5 VDC GND *See note. *See note.
Supply Voltage. Nominally 5.0 VDC. Supply Ground. Nominally 0.0 VDC. Serial Data Input. Equivalent to Si5020 DIN+ and DIN-, respectively.* Reference Clock Input. Equivalent to Si5020 REFCLK+ and REFCLK-, respectively.* Lock Detect Output. Driven high when Si5020 is locked to serial data input signal. Driven low when out of lock. This signal is an inverted and level shifted version of the Si5020 LOL output.* Serial Data Output. Equivalent to Si5020 DOUT- and DOUT+, respectively.* Serial Clock Output. Equivalent to Si5020 CLKOUT- and CLKOUT+, respectively.*
16
O
TTL
18, 19
SERDATON, SERDATOP SERCLKON, SERCLKOP
O
*See note.
22, 23
O
*See note.
Rev. 1.0
9
SI5020C-BA
Pin # 24 Pin Name RATESEL1 I/O I Signal Level LVTTL Description Rate Select 1. Equivalent to Si5020 RATESEL0 input. The RATESEL0 and RATESEL1 pins on the Si5020CBA board are swapped with respect to those on the Si5020 device.* Rate Select 0. Equivalent to Si5020 RATESEL1 input. The RATESEL0 and RATESEL1 pins on the Si5020CBA board are swapped with respect to those on the Si5020 device.*
31
RATESEL0
I
LVTTL
*Note: Refer to the Si5020 data sheet for details.
10
Rev. 1.0
SI5020C-BA
Ordering Guide
Table 5. Ordering Guide Part Number SI5020C-BA Package See Package Outline Temperature -40 to 85 C
Rev. 1.0
11
SI5020C-BA
Package Outline: SI5020C-BA
Figure 2 illustrates the package details for the SI5020C-BA. Table 6 lists the values for the dimensions shown in the illustration.
Figure 2. SI5020C-BA Mechanical Drawing Table 6. Package Diagram Dimensions (mm)
Dimension A A1 A2 C D e E h L P R2 W Description Total Card Height Card Thickness Height to Pick Point Offset to Pick Point Body Size Pad Pitch Total Pad Pitch Castellation Width Pad Length Diameter of Pick Area Pad Radius Pad Width 0.34 1.10 -- 0.23 0.45 Minimum 1.97 0.80 1.65 1.32 8.95 Nominal 2.12 0.85 1.75 1.35 9.05 0.80 BSC. 5.60 REF. 0.39 1.20 3.50 0.25 0.50 0.44 1.30 -- 0.27 0.55 Maximum 2.27 0.90 1.85 1.38 9.15
12
Rev. 1.0
SI5020C-BA
Document Change List
Revision 0.81 to Revision 0.9
! !
Removed all references to Si5020-BA. Changed reference of in-system evaluation board to micro PCB. ! Front Page:
Micro PCB graphic updated. Pin assignment drawing updated. " Features, Applications, and Description sections updated.
" "
! !
"Functional Description" on page 7 updated. "Voltage Regulator Circuit" on page 7 updated.
Revision 0.90 to Revision 1.0
!
Updated "Package Outline: SI5020C-BA" on page 12.
Rev. 1.0
13
SI5020C-BA
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
14
Rev. 1.0

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